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IBM brings CO nanotube-based computers a step closer

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IBMs technique can arrange singular CO nanotubes -- and infrequently pairs -- between dual electrical contacts. Its an essential partial of creation a transistor in that a nanotube leads from a source on one side to a empty on a other. At left in this is an picture of a chip designed to exam a record electrically; during right is a close-up of a nanotubes stretching from one electrical hit to another.

IBM’s technique can arrange singular CO nanotubes — and infrequently pairs — between dual electrical contacts. It’s an essential partial of creation a transistor in that a nanotube leads from a source on one side to a empty on a other. At left in this is an picture of a chip designed to exam a record electrically; during right is a close-up of a nanotubes stretching from one electrical hit to another.


(Credit:
IBM)

In a bid to find a deputy for today’s silicon chips, IBM researchers have pushed CO nanotube record a poignant step ahead.

Carbon nanotubes are really little structures done of a hideaway of CO atoms rolled into a cylindrical shape, and a group of 8 researchers have figured out a proceed to precisely place them on a mechanism chip, IBM announced today. That growth allows them to arrange a nanotubes 100 times some-more densely than progressing methods, a pivotal step in careful chipmaking, and IBM has built a chip with some-more than 10,000 CO nanotube-based elements.

The new technique helps urge a nanotubes’ chances in a hunt for alternatives once today’s silicon transistor record runs out of steam. Today’s chips are done of little electrical switches called transistors, and CO nanotubes are a intensity surrogate for a silicon channels that lift electrical stream in those transistors.

Moore’s Law has successfully softened microchips for decades by timorous chip elements to ever-smaller sizes, and it’s got years of life nonetheless in it. Today’s Intel “Ivy Bridge” Core processors found in new PCs have transistor elements measuring 22 nanometers, or billionths of a meter, and Intel thinks it can cringe that over several generations of alleviation down to 5 nanometers. Beyond that, though, processors will substantially need to be built with really opposite technology.

IBM’s self-assembling nanotube chip tech (pictures)

Carbon nanotubes (CNTs) can have silicon’s semiconductor nature, giving them a on-again off-again electrical abilities essential to creation chip transistors. And they have a glorious ability to broadcast electrons when switched on. But they’ll be unreal for mechanism chips unless chipmakers can find a proceed to place them really precisely and in vast quantities.

IBM’s research, published currently in a biography Nature Nanotechnology, uses a mixed of chemical tricks that collectively meant chipmakers can place sold nanotubes where they wish in special trenches. And they reached a firmness of a billion nanotubes per block centimeter when constructing their CO nanotube field-effect transistor (CNTFET) devices.

“This new ability to accurately place individual, aligned CNTs during a high firmness enables a phony of a vast series of single-CNT transistors,” a researchers pronounced in a paper. “Using a chain method, we built arrays of CNTFETs (designed with one ditch per channel of a device) and electrically characterized some-more than 10,000 CNT inclination on a singular chip.”

Carbon nanotubes uncover promise, though they’re usually one claimant for a ostensible post-silicon epoch of computing. Other options embody skinny ribbons of CO lattices called graphene that are closely associated to CO nanotubes; relocating from silicon to other elements including indium, arsenic, and gallium; silicon photonics, that uses light instead of electrons to broadcast information; spintronics, that uses an nucleus skill spin instead of a charge; and even some-more outlandish possibilities such as DNA computers and quantum computing.

IBM researcher Hongsik Park looks over a chip wafer with CO nanotubes. The wafer has dual surfaces, trenches done of hafnium oxide that attract CO nanotubes in a special resolution silicon oxide that doesnt.

IBM researcher Hongsik Park looks over a chip wafer with CO nanotubes. The wafer has dual surfaces, trenches done of hafnium oxide that attract CO nanotubes in a special resolution silicon oxide that doesn’t.


(Credit:
IBM)

The IBM Research paper is created by Hongsik Park, Ali Afzali, Shu-Jen Han, George S. Tulevski, Aaron D. Franklin, Jerry Tersoff, James B. Hannon, and Wilfried Haensch, and their proceed requires mixed techniques.

The initial step is scheming a wafer — a same simple substrate used to build required microprocessors today. One covering on tip consists of hafnium oxide, and afterwards on tip of that is a sold settlement of silicon dioxide. IBM’s proceed leaves skinny channels in a silicon dioxide where a hafnium oxide is exposed.

The hafnium oxide is afterwards coated with an intensely skinny covering of a chemical called — prop yourself — 4-(N- hydroxycarboxamido)-1-methylpyridinium iodide. That’s NMPI for short.

The subsequent step is scheming a nanotubes. They’re wrapped in a soaplike chemical called a surfactant called sodium dodecyl sulfate that lets them be dissolved into water, afterwards a wafer is enthralled in a solution.

The surfactant and a NMPI attract any other chemically, contracting a CO nanotubes to a hafnium oxide trenches. IBM’s routine can be used to place a nanotubes, rightly aligned, into a grid of slight trenches. The trenches are 200nm detached in one dimension and 500nm detached in a other dimension, that is how IBM gets a firmness of a billion nanotubes per block centimeter.

The dim lines are CO nanotubes that infrequently -- though not always -- are placed in trenches. The some-more accurately IBM can place a nanotubes, a some-more expected they can be used as semiconductor inclination in mechanism chips.

The dim lines are CO nanotubes that infrequently — though not always — are placed in trenches. The some-more accurately IBM can place a nanotubes, a some-more expected they can be used as semiconductor inclination in mechanism chips.


(Credit:
IBM)

IBM also built a apart device that indeed connected a CO nanotubes so their properties could be totalled electrically.

IBMs silicon wafers have dual surfaces on top, hafnium oxide and silicon dioxide. This close-up picture shows speckles of CO nanotubes that bond usually with a hafnium oxide, partial of IBMs proceed to positioning them precisely on a chip.

IBM’s silicon wafers have dual surfaces on top, hafnium oxide and silicon dioxide. This close-up picture shows speckles of CO nanotubes that bond usually with a hafnium oxide, partial of IBM’s proceed to positioning them precisely on a chip.


(Credit:
IBM)

IBM isn’t earnest a technique will be commercially viable, though some confidence shows by in a paper — in sold since a routine is concordant with stream chipmaking technology.

“This new chain technique is straightforwardly implemented, involving common chemicals and processes, and provides a height for destiny CNTFET initial studies,” a paper said. “Furthermore, these formula uncover that CNT chain around chemical self-assembly is a earnest proceed for building a viable CNT proof record concordant with existent semiconductor fabrication.”

Article source: http://news.cnet.com/8301-11386_3-57541381-76/ibm-brings-carbon-nanotube-based-computers-a-step-closer/


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